1. Field of the Invention
The invention relates generally to interfacing circuitry and technique and, more particularly, to asynchronous data transfer between two different clock domains.
2. Description of the Related Art
In an ideal world, all devices communicating with one another would be synchronized to one clock, so that no timing problems occur in such communications. In a real world, however, this is not always possible. Many different devices communicating with one another reside in different clock domains, meaning that they are synchronized to different clocks with different frequencies. Even in a simple computer system, many different components thereof reside in different clock domains. For example, a CPU could be operating at a much higher frequency than other components in the system with which the CPU is communicating.
Whenever two devices reside in two different clock domains, the two devices can communicate either asynchronously or synchronously. In a synchronous approach, the clocks in the two domains are synchronized to a third clock domain.
Asynchronous data transfer between two different clock domains could introduce potential problems such as data mis-sampling. For example, when a high speed device configuration register (DCR) operating at 200 MHz or faster transfers data to and/or from an extremely low speed peripheral device such as an interface to a serial erasable programmable read-only memory (SEPROM) operating at 32 KHz or slower, there could be potential problems such as data mis-sampling.
One possible solution is to implement an interlock mechanism. For example, data acknowledgement may be used to notify the devices in communication of timing information on a read/write process. However, if a timeout mechanism in the data-acknowledge polling system exists and the frequency ratio between the two domains is too large, there could be a potential timeout in the acknowledge polling process and the communication between the two domains would be lost.
Therefore, there is a need for access management to coordinate data transfer between two clock domains without causing a timeout no matter how different the two frequencies in the clock domains are.